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ZNSI-TR-2025-06 v2Silicon

Wafer-Scale Defect Tolerance by Synaptic Rerouting

Kenji Arakawa, Mireille Achterberg, Priya Raghunathan-Holt, Haruto Ishida

Abstract

A 300 mm wafer always has defects, and a wafer-scale chip cannot discard the dies that hold them. We show that the plasticity KIRIN uses for learning also routes around defects: synapses into a dead die stop carrying spikes, weaken, and are replaced by neighbours that do. With rerouting enabled during burn-in, usable yield of KIRIN-9 wafers at Site 7 rose from 34% to 91%.

1. The yield problem

Conventional chips are cut from the wafer and the bad ones thrown away. KIRIN-9 stitches 88 dies into one continuous neuron sheet, so a single dead die used to mean a dead wafer. At KIRIN-7 volumes this was tolerable. At KIRIN-9 volumes it was not.

2. Rerouting

During burn-in the wafer is run on a synthetic curriculum while plasticity is on. Paths through a defective die never complete, so their eligibility traces never convert into potentiation, and the synapses decay. Neighbouring paths that do complete strengthen in their place. The wafer is not told where its defects are. It finds them.

KIRIN-9 wafer map: 88 dies, five rerouted around defects and one fused.
FIG. 1 Burn-in map of wafer K9-0412-C after 36 hours. Red dies are routed around; the dark die is fused.

3. Results at Site 7

Of 2,412 KIRIN-9 wafers started in the first half of 2026, 2,195 passed burn-in. Wafers that failed were not scrapped. Their working dies were harvested and, after reconditioning, joined to wafers that had passed, where they were absorbed into the existing synaptic map within a day. We do not yet fully understand why harvested dies integrate so readily.

Rerouting continues in service. A KIRIN-9 wafer in a Shōgi pod reroutes, on average, around 0.4 newly failed neurons per second, with no measurable effect on MUGEN.

Revision history

  • v2, August 2026. Section 3 replaces pre-production results with Site 7 production figures for the first half of 2026, and reference [3] is added. The method is unchanged.
  • v1, June 2025. First publication, with results from KIRIN-9 pre-production wafers.

References

  1. Arakawa, K., Ishida, H. (2023). Conductance drift as a learning signal in memristive crossbars. ZNSI-TR-2023-04.
  2. Achterberg, M. (2024). Site 7 burn-in protocol, revision 11. ZNSI internal.
  3. Okonkwo-Reyes, I., et al. (2025). Plastic inference. ZNSI-TR-2025-09.